Semiconductors form the basis of modern electronics. Possessing physical properties that can be selectively modified and controlled between conduction and insulation, semiconductors are essential in most modern electrical devices (e.g., computers, cellular phones, photovoltaic cells, etc.). Group IV semiconductors generally refer to those elements in the fourth column of the periodic table (e.g., carbon, silicon, germanium, etc.).
In general, a solid semiconductor tends to exist in three forms: crystalline, polycrystalline, and amorphous. In crystalline form, semiconductor atoms are positioned in a single unbroken crystal lattice with no grain boundaries. In polycrystalline form, the semiconductor atoms are positioned in many smaller and randomly oriented crystallites (smaller crystals). The crystallites are often referred to as grains. In amorphous form, the semiconductor atoms show no long-range positional order.
In general, conduction generally refers to the movement of electrically charged carriers, such as electrons or holes (i.e., lack of electrons), through electromagnetic fields. Metals tend to have substantial amounts of electrically charged particles available, whereas insulators have very few.
In the absence of impurities (called dopants), a semiconductor tends to behave as insulator, inhibiting the flow of an electric current. However, after the addition of relatively small amounts of dopants, the electrical characteristics of a semiconductor can dramatically change to a conductor by increasing the amount of electrically charged carriers. For example, in a process called photoexcitation, absorbed light will generally create an electron-hole pair (photocarriers) that in turn tends to increase overall conductivity (photoconductivity).
Depending on the kind of impurity, a doped region of a semiconductor can have more electrons (n-type) or more holes (p-type). For example, in a common configuration, a p-type region is placed next to an n-type region in order to create a (p-n) junction with a “built-in” potential. That is, the energy difference between the two Fermi levels.
Under generally accepted principles of quantum mechanics, electrons of an atom can only reside in certain states, so that only particular energy levels are possible. However, the occupation of particular energy states cannot be determined with particularity. Consequently, for an ensemble of atoms (e.g., solid) a probability distribution or density is commonly used, which for electrons is called the Fermi distribution. In general, the Fermi level describes the energy level at a given temperature in which ½ of the energy states are filled. Energy states are unique and correspond to a quantum number.
Consequently, electrons on the p-type side of the junction within the electric field may then be attracted to the n-type region and repelled from the p-type region, whereas holes within the electric field on the n-type side of the junction may then be attracted to the p-type region and repelled from the n-type region. Generally, the n-type region and/or the p-type region can each respectively be comprised of varying levels of relative dopant concentration (often shown as n−, n+, n++, p−, p+, p++, etc.). The built-in potential and thus magnitude of electric field generally depend on the level of doping between two adjacent layers.
There are several methods that can be used to provide doped layers to form a p/n junction or a hi-lo (e.g., p+/p or n+/n) junction. One set of such methods involves providing a high dopant concentration at the wafer surface, and a subsequent high temperature step (e.g., between about 800° C. and about 1000° C.) to diffuse dopants from the surface into the wafer. For example, the process can be performed in a dopant-containing ambient, such as e.g. POCl3. Alternatively a dopant containing glass can be deposited on the wafer surface and then heated to a high temperature for the dopant diffusion to occur. Another method, which tends to be more expensive, is to implant the dopants using a high energy dopant ion beam followed by a quick high temperature annealing step to activate the dopant atoms. However, although dopant dosage may be controlled with high precision, ion implantation tends to be relatively expensive due to the use of specialized semiconductor manufacturing equipment.
Another approach to providing doped layers on silicon wafers is to deposit a doped silicon layer, typically using chemical-vapor-deposition (CVD) techniques, such as, e.g., conventional CVD, plasma-enhanced CVD (PECVD), or hot-wire CVD (HWCVD). Depending on the growth conditions, epitaxial, polycrystalline, or amorphous films can be grown. These approaches tend to be relatively expensive due to expensive vacuum equipment. Also, these methods tend to suffer from low deposition rates that are required to provide high quality films.
In addition, another problem associated with the listed approaches is the inability to easily pattern the deposited silicon film. The most straightforward way to provide patterns with the above approaches would be to use photolithography, which tends to be relatively expensive. Alternatively, screen printing of doped pastes can be used. However, in this process, the downward mechanical force of the printing squeegee also tends to subject the substrate to stress, and hence may detrimentally affect the electrical and physical characteristics of the substrate. For devices that require multiple deposition steps, such as a back contact solar cell, the stress is aggravated. In general, every additional screen printing step tends to reduce the process yield (and increase costs) due to damage or breakage. Additionally, alignment of the screen pattern may also present substantial challenges. For example, if pattern alignment is poor, the resulting solar cells may malfunction (e.g., short) further reducing process yield.
In addition to providing doped silicon layers, these layers as well as the silicon substrate have to be properly passivated in order to reduce recombination losses in the solar cell. Unpassivated surfaces contain a large number of unsaturated bonds which create deep energy levels that assist recombination of minority carriers in the semiconductor.
One of the widely used approaches for passivation of wafer surfaces is to deposit a film of dielectric (e.g., SiO2, SiNx, etc.), which may reduce the density of deep states at the interface and/or provide an electric field at that interface (see, e.g., A. Aberle, Prog. Photovolt: Res. Appl. 8, p. 473 (2000)).
In some examples described in prior art, processes of oxidation and nitridation have been used to passivate internal surfaces of porous silicon layers, which were prepared by conventional electrochemical anodization on heavily diffused silicon wafers, see e.g. L. Debarge et al, Materials Science in Semiconductor Processing 1, 281 (1998) and L. Stalmans et al, Solar Energy Materials & Solar Cells 58, 237 (1999).
In other examples, an approach for fabricating a heterojunction (an interface between two layers of dissimilar semiconductors) at an interface with an emitter, back surface field (BSF), and/or a contact, in order to reduce recombination at that interface is provided. Typically, using heterojunction interfaces with an additional energy barrier due to band offset between interfacing materials can reduce recombination at that interface (e.g., in a heterojunction with intrinsic thin-layer (HIT) cell). In certain embodiments, a nanoparticle material with silicon nanoparticles embedded into the matrix of an insulator (e.g., SiOx, SiOxNy, etc.) can be utilized. For example, by using Semi-Insulating Polysilicon (SIPOS) materials that have relatively high oxygen content, a band gap (e.g., 1.5 eV) wider than that of crystalline silicon, 1.12 eV, can be provided.
SIPOS materials are generally prepared by a variety of chemical vapor deposition (CVD) methods, and can include silicon nanocrystals embedded within a matrix of SiO2. Such a structure may be doped to have high conductivity (e.g., 103 S/cm), and with a larger band gap than silicon. For example, an open circuit voltage (Voc) of about 720 mV can be achieved using SIPOS to form an emitter on a silicon wafer (see, e.g., E. Yablonovitch, et al, Applied Physics Letters 47(11), p. 1211 (1985)).
In view of the foregoing, there is desired a method of providing doped silicon layers with the passivating properties to form junctions and devices therefrom.